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D a t a S h e e t , Rev. 1.0, O c t . 2 0 0 4
HYS64T128020HM-3.7-A HYS64T128020HM-5-A
214-Pin Micro-DIMM-DDR2-SDRAM Modules MDIMM DDR2 SDRAM RoHS Compliant
Memory Products
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The information in this document is subject to change without notice. Edition 2004-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S h e e t , Rev. 1.0, O c t . 2 0 0 4
HYS64T128020HM-3.7-A HYS64T128020HM-5-A
214-Pin Micro-DIMM-DDR2-SDRAM Modules MDIMM DDR2 SDRAM RoHS Compliant
Memory Products
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stop
thinking.
HYS64T128020HM-[3.7/5]-A Revision History: Previous Revision: Page All 19 26 all Rev. 1.0 Rev. 0.5 2004-10 2004-04
Subjects (major changes since last revision) Only green products included IDD current defined SPD Codes added editorial change
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.3_2004-01-14.fm
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Table of Contents 1 1.1 1.2 2 2.1 3 3.1 3.2 4 4.1 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Product Type Nomenclature (DDR2 DRAMs and DIMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data Sheet
5
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
214-Pin Micro-DIMM-DDR2-SDRAM Modules MDIMM
HYS64T128020HM-3.7-A HYS64T128020HM-5-A
1
Overview
This chapter gives an overview of the 214-Pin Micro-DIMM-DDR2-SDRAM Modules product family and describes its main characteristics.
1.1
*
Features
* * * * * * * * Burst Refresh, Distributed Refresh and Self Refresh All inputs and outputs SSTL_1.8 compatible OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Serial Presence Detect with E2PROM Micro-DIMM Dimensions (nominal) : 30 mm high, 54.0 mm wide Based on JEDEC standard reference layouts Raw Card "B" 2-piece type Mezzanine Socket with 0,4 mm contact centers RoHS Compliant Products1)
* *
* *
214-Pin PC2-4200 and PC2-3200 DDR2 SDRAM memory modules for use as main memory when installed in systems such as mobile personal computers. 128M x 64 module organisation and 64M x16 chip organisation JEDEC standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply Built with 1 Gb DDR2 SDRAMs in P-TFBGA-92 chipsize packages Programmable CAS Latencies (3, 4 and 5), Burst Length (8 & 4) and Burst Type Performance -3.7
Table 1
Product Type Speed Code Speed Grade max. Clock Frequency @CL5 @CL4 @CL3 min. RAS-CAS-Delay min. Row Precharge Time min. Row Active Time min. Row Cycle Time
-5 PC2-3200 3-3-3 200 200 200 15 15 40 55
Units -- MHz MHz MHz ns ns ns ns
PC2-4200 4-4-4
fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
266 266 200 15 15 45 60
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Data Sheet
6
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Overview
1.2
Description
The memory array is designed with 1 Gb Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The INFINEON HYS64T128020HM-[3.7/5]-A module family are low profile Unbuffered Micro-DIMM modules "MDIMMs" with 30,0 mm height based on DDR2 technology. DIMMs are available as 128M x 64 organisation and density, intended for mounting into 214-pin mezzanine connector sockets.
Table 2
Ordering Information Compliance Code2) Description SDRAM Technology 1 Gbit (x16) 1 Gbit (x16)
Product Type1) HYS64T128020HM-3.7-A HYS64T128020HM-5-A
1GB 2Rx16 PC2-4200M-444-11-A0 two ranks 1 GByte DIMM 1GB 2Rx16 PC2-4200M-444-11-A0 two ranks 1 GByte DIMM
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS64T128020HM-3.7-A, indicating Rev. "A" dies are used for DDR2 SDRAM components. For all INFINEON DDR2 module and component nomenclature see Chapter 7 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, e.g. "PC2-4200M-444-11-A0, where 4200M means Micro-DIMM modules with 4.26 GB/sec Module Bandwidth and "444-11" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "A".
Table 3
Address Format
DIMM Density Module Organization Memory Ranks # of SDRAMs # of row/bank/column bits Raw Card 1 GByte Table 4 128M x 64 2 8 13/3/10 A
Components on Modules1) DRAM Components2) HYB18T1G160AF HYB18T1G160AF DRAM Density 1 Gbit 1 Gbit DRAM Organisation 64M x 16 64M x 16
Product Type2) HYS64T128020HM-3.7-A HYS64T128020HM-5-A
2) Green Product
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Data Sheet
7
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration
2
Pin Configuration
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in Table 5 (214 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1. Table 5 Pin# Clock Signals 122 194 123 195 CK0 CK1 CK0 CK1 I I I I SSTL SSTL SSTL SSTL Clock Signals CK 1:0, Complement Clock Signals CK 1:0 Note: The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and the falling edge of CK. A Delay Locked Loop (DLL) circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. Pin Configuration of MDIMM Name Pin Type Buffer Type Function
43 147
CKE0 CKE1
I I
SSTL SSTL
Clock Enables 1:0 Note: Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK signal when LOW. By deactivating the clocks, CKE0 initiates the Power Down Mode or the Self Refresh Mode. Note: 2-rank module Note: 1-rank module
NC Control Signals 165 62 S0 S1
NC I I SSTL SSTL
Chip Select Rank 1:0 Note: Enables the associated DDR2 SDRAM command decoder when LOW and disables the command decoder when HIGH. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by S1. The input signals also disable all outputs (except CKE and ODT) of the register(d) on the DIMM when both inputs are high. When S is HIGH, all register outputs (except CK, ODT and Chip select) remain in the previous state. Note: 2-rank module Note: 1-rank module
NC 163 60 56 RAS CAS WE
NC I I I SSTL SSTL SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE) Note: When sampled at the cross point of the rising edge of CK,and falling edge of CK, RAS, CAS and WE define the operation to be executed by the SDRAM. Bank Address Bus 1:0 Note: Select internal SDRAM memory bank
Address Signals 55 162 BA0 BA1 I I SSTL SSTL
Data Sheet
8
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 46 Pin Configuration of MDIMM (cont'd) Name BA2 NC 161 159 52 158 51 50 157 48 155 154 54 47 153 167 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC Pin Type I NC I I I I I I I I I I I I I I I NC Buffer Type SSTL - SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL - Address Input 13 Note: modules based on x4/x8 component Note: modules based on x16 component Function Bank Address Bus 2 Note: greater than 512Mb DDR2 SDRAMS Note: less than 1Gb DDR2 SDRAMS Address Inputs 12:0, Address Input 10/Autoprecharge Note: During a Bank Activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is selected and BA[2:0] defines the bank to be precharged. If AP is LOW, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[2:0] to control which bank(s) to precharge. If AP is HIGH, all banks will be precharged regardless of the state of BA[2:0] inputs. If AP is LOW, then BA[2:0] are used to define which bank to precharge.
Data Sheet
9
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# Data Signals 3 4 9 10 109 110 114 115 12 13 21 22 117 118 125 126 24 25 30 31 128 129 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Note: Data Input/Output pins Pin Configuration of MDIMM (cont'd) Name Pin Type Buffer Type Function
Data Sheet
10
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 133 134 33 34 38 39 136 137 142 143 67 68 73 74 174 175 179 180 76 77 81 82 182 183 188 189 84 85 92 93 191 192 200 201 95 96 101 102 203 204 Pin Configuration of MDIMM (cont'd) Name DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Function Data Bus 63:0
Data Sheet
11
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# 208 209 7 6 19 18 28 27 140 139 71 70 186 185 198 197 99 98 112 120 131 36 177 79 90 206 EEPROM 105 SCL I CMOS Serial Bus Clock Note: This signal is used to clock data into and out of the SPD EEPROM. 104 SDA I/O OD Serial Bus Data Note: This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected from SDA to VDDSPD on the motherboard to act as a pull-up. 211 213 SA0 SA1 I I CMOS CMOS Serial Address Select Bus 1:0 Note: Address pins used to select the Serial Presence Detect base address. I/O Reference Voltage Note: Reference voltage for the SSTL-18 inputs. Pin Configuration of MDIMM (cont'd) Name DQ62 DQ63 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Masks 7:0 Note: The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is LOW but blocks the write operation if it is HIGH. In Read mode, DM lines have no effect. Note: x8 based module Data Strobes 7:0 Note: The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sourced by the DDR2 SDRAM and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. Note: See block diagram for corresponding DQ signals Function Data Bus 63:0
Power Supplies 1
VREF
AI
-
Data Sheet
12
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration Table 5 Pin# Pin Configuration of MDIMM (cont'd) Name Pin Type PWR Buffer Type - Function Power Supply Note: Power and ground for the DDR SDRAM
42, 45, 49, 53, VDD 57, 61, 64, 146, 149, 152, 156, 160, 164, 168, 171 107
VDDSPD
PWR
-
EEPROM Power Supply Note: Serial EEPROM positive power supply, wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt.
2, 5, 8, 11, 14, VSS 17, 20, 23, 26, 29, 32, 35, 37, 40, 66, 69, 72, 75, 78, 80, 83, 86, 89, 91, 94, 97, 100, 103, 108, 111, 113, 116, 119, 121, 124, 127, 130, 132, 135, 138, 141, 144, 173, 176, 178, 181, 184, 187, 190, 193, 196, 205, 199, 202, 207, 210 Other Pins 166 63 ODT0 ODT1
GND
-
Ground Plane Note: Power and ground for the DDR SDRAM
I I
SSTL SSTL
On-Die Termination Control 1:0 Note: Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM mode register. Note: 2-rank module Note: 1-rank module
NC 15, 16, 41, 44, NC 58, 59, 65, 87, 88, 106, 145, 148, 150, 151, 167, 169, 170, 172, 212, 214 NC -
Not connected Note: Pins not connected on Infineon MDIMMs
Data Sheet
13
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration
Table 6 Abbreviation I O I/O AI PWR GND NC
Abbreviations for Pin Type Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
Table 7 Abbreviation SSTL
Abbreviations for Buffer Type Description Serial Stub Terminated Logic (SSTL_18) CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
CMOS
OD
Data Sheet
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Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration
DQ0 VSS DQS0 DQ2
VREF - Pin 001 - Pin 003 - Pin 005 - Pin 007 - Pin 009 Pin Pin Pin Pin 011 013 015 017
V SS - Pin 002 DQ1 - Pin 004 DQS0 - Pin 006 V SS DQ3 DQ8 V SS Pin 008 Pin 010 Pin 012
Pin 109 - DQ4 Pin 111 - V SS Pin 113 - V SS Pin 115 - DQ7 Pin 117 - DQ12 Pin 119 - V SS Pin Pin Pin Pin 121 123 125 127 - V SS - CK0 - DQ14 - V SS
Pin 108 - VSS Pin 110 - DQ5 Pin 112 - DM0 Pin 114 - DQ6 Pin 116 - VSS Pin Pin Pin Pin 118 120 122 124 DQ13 DM1 CK0 VSS
VSS DQ9 NC VSS
DQS1 - Pin 019 DQ10 - Pin 021 VSS - Pin 023 DQ17 - Pin 025 DQS2 - Pin 027 VSS - Pin 029 DQ19 - Pin 031 DQ24 - Pin 033 VSS - Pin 035 VSS - Pin 037 DQ27 - Pin 039 NC - Pin 041 CKE0 - Pin 043 VDD - Pin 045 A11 VDD A4 VDD Pin Pin Pin Pin 047 049 051 053
Pin 014 NC - Pin 016 DQS1 - Pin 018 V SS - Pin 020 DQ11 - Pin 022 DQ16 - Pin 024 V SS - Pin 026 DQS2 DQ18 V SS DQ25 DM3 DQ26 V SS VDD Pin Pin Pin Pin Pin Pin Pin Pin 028 030 032 034 036 038 040 042
Pin 129 - DQ21 Pin 131 - DM2 Pin 133 - DQ22 Pin Pin Pin Pin Pin Pin Pin Pin 135 137 139 141 143 145 147 149 V SS DQ29 DQS3 V SS DQ31 NC CKE1/NC V DD
Pin 126 - DQ15 Pin 128 - DQ20 Pin 130 - VSS Pin 132 - VSS Pin 134 - DQ23 Pin 136 - DQ28 Pin 138 - VSS Pin Pin Pin Pin 140 142 144 146 DQS3 DQ30 VSS
NC - Pin 044 NC/BA2 - Pin 046 A7 - Pin 048 A5 A2 A10/AP WE NC CAS S1/NC VDD Pin Pin Pin Pin Pin Pin Pin Pin 050 052 054 056 058 060 062 064
Pin 151 - NC Pin 153 - A12 Pin 155 - A8 Pin Pin Pin Pin Pin Pin Pin Pin 157 159 161 163 165 167 169 171 A6 A1 A0 RAS S0 NC NC V DD
VDD Pin 148 - NC Pin 150 - NC Pin 152 - VDD Pin 154 - A9 Pin 156 - VDD Pin 158 - A3 Pin 160 - VDD Pin Pin Pin Pin 162 164 166 168 BA1 VDD ODT0
BA0 - Pin 055 VDD - Pin 057 NC - Pin 059 VDD - Pin 061 ODT1/NC - Pin 063 NC - Pin 065 DQ32 - Pin 067 VSS DQS4 DQ34 VSS Pin Pin Pin Pin 069 071 073 075
V SS - Pin 066 DQ33 - Pin 068 DQS4 - Pin 070 V SS DQ35 DQ40 V SS V SS DQ43 DQ48 V SS NC DM6 DQ50 V SS Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin 072 074 076 078 080 082 084 086 088 090 092 094
Pin 173 - V SS Pin 175 - DQ37 Pin 177 - DM4 Pin Pin Pin Pin Pin Pin Pin Pin 179 181 183 185 187 189 191 193 DQ38 V SS DQ45 DQS5 V SS DQ47 DQ52 V SS
VDD Pin 170 - NC Pin 172 - NC Pin 174 - DQ36 Pin 176 - VSS Pin 178 - VSS Pin 180 - DQ39 Pin 182 - DQ44 Pin Pin Pin Pin 184 186 188 190 VSS DQS5 DQ46
DQ41 - Pin 077 DM5 - Pin 079 DQ42 - Pin 081 VSS - Pin 083 DQ49 - Pin 085 NC - Pin 087 VSS - Pin 089 VSS DQ51 DQ56 VSS Pin Pin Pin Pin 091 093 095 097
Pin 195 - CK1 Pin 197 - DQS6 Pin 199 - V SS Pin 201 - DQ55 Pin 203 - DQ60 Pin 205 - V SS Pin 207 - V SS Pin 209 - DQ63 Pin 211 - SA0 Pin 213 - SA1
DQS7 - Pin 099 DQ58 - Pin 101 VSS - Pin 103 SCL - Pin 105 V DDSPD - Pin 107
DQ57 - Pin 096 DQS7 - Pin 098 V SS - Pin 100 DQ59 - Pin 102 SDA - Pin 104 NC - Pin 106
VSS Pin 192 - DQ53 Pin 194 - CK1 Pin 196 - VSS Pin 198 - DQS6 Pin 200 - DQ54 Pin 202 - VSS Pin 204 - DQ61 Pin Pin Pin Pin 206 208 210 212 DM7 DQ62 VSS
NC Pin 214 - NC MPPT0060
Figure 1
Pin Configuration for Two-Piece Mezzanine Socket on MDIMM (214 pins)
Data Sheet
15
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Pin Configuration
2.1
BA0 - BA1 A0 - An RAS CAS WE CKE0 CKE1 ODT0 ODT1 CK0 CK0 CK1 CK1 S0 S1 DM0 DQS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1 DQS1 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Block Diagrams
BA0 - BA1: SDRAMs D0 - D7 A0 - An: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 CKE0: SDRAMs D0 - D3 CKE1: SDRAMs D4 - D7 ODT0: SDRAMs D0 - D3 ODT1: SDRAMs D4 - D7 4 loads 4 loads VDD,SPD VDD/VDDQ VREF VSS VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D7 VREF: SDRAMs D0 - D7 VSS: SDRAMs D0 - D7 SCL SDA SA0 SA1 VSS VSS SCL SDA A0 A1 A2 WP E0
CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
D0
CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
D4 DM4 DQS4 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5 DQS5 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D5 DM6 DQS6 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 DQS7 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
D2
CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CS LDM LDQS LDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDM UDQS UDQS I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15
D6
D1
D3
D7
DM2 DQS2 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3 DQS3 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
MPBT0010
Figure 2 Notes
Block Diagram Raw Card A Micro DIMM (x64, 2 Ranks, x16) 2. S0, S1, BAn, An, RAS, CAS, WE, ODTO, ODT1, CKEO, CKE1 resistors are 3 5 %
1. DQ, DQS, DM resistors are 22 5 %
Data Sheet
16
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
IDD Specifications and Conditions
3
Table 8 Parameter
IDD Specifications and Conditions
IDD Measurement Conditions1)2)3)4)5)6)
Symbol
Operating Current 0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD0
Operating Current 1 IDD1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2N
IDD2P
Precharge Quiet Standby Current IDD2Q All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL.MIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA. Operating Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL.MIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
Operating Current IDD4W Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL.MIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current IDD5B tCK = tCK.MIN, Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Refresh Current IDD5D tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Data Sheet
17
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
IDD Specifications and Conditions Table 8 Parameter Self-Refresh Current CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max.
IDD Measurement Conditions1)2)3)4)5)6)
Symbol
IDD6
All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD: LOW is defined as VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
STABLE is defined as: inputs are stable at a HIGH or LOW level FLOATING is defined as: inputs are VREF = VDDQ /2 SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes.
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 6) For details and notes see the relevant INFINEON component data sheet
Data Sheet
18
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
IDD Specifications and Conditions
Table 9
IDD Specification for HYS64T128020HM-[-3.7/-5]-A
HYS64T128020HM-3.7-A HYS64T128020HM-5-A Unit Notes
Organization
Product Type
1 GB 2 Ranks x64 -3.7
1 GB 2 Ranks x64 -5 Max. 320 380 40 280 220 100 40 320 440 540 740 60 32 1040 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
1)
1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1) 1)
Symbol
Max. 340 400 40 370 260 140 50 400 540 680 760 60 32 1100
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P( MRS = 0) IDD3P( MRS = 1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6(L) IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled.
Data Sheet
19
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
IDD Specifications and Conditions
3.1
IDD Test Conditions
For testing the IDD parameters, the timing parameters as in Table 10 are used. Table 10 Parameter CAS Latency
IDD Measurement Test Conditions
Symbol -3.7 4 3.75 15 60 10 45 70000 15 127.5 7.8 -5 3 5 15 55 10 40 70000 15 127.5 7.8 Unit PC2-4200-4-4-4 PC2-3200-3-3-3
CL(IDD) Clock Cycle Time tCK(IDD) Active to Read or Write delay tRCD(IDD) Active to Active / Auto-Refresh command period tRC(IDD) Active bank A to Active bank B command delay tRRD(IDD) Active to Precharge Command tRAS.MIN(IDD) tRAS.MAX(IDD) Precharge Command Period tRP(IDD) Auto-Refresh to Active / Auto-Refresh command period tRFC(IDD) Average periodic Refresh interval tREFI
tCK
ns ns ns ns ns ns ns ns s
3.2
On Die Termination (ODT) Current
current consumption for any terminated input pin, depends on the input pin is in tri-state or driving 0 or 1, as long a ODT is enabled during a given period of time.
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A[6,2] in the EMRS(1) a "weak" or "strong" termination can be selected. The Table 11 Parameter ODT current per terminated pin
Symbol Min. 5 2.5 10 5
Typ. 6 3 12 6
Max. Unit 7.5 3.75 15 7.5
EMRS(1) State
Enabled ODT current per DQ IODTO ODT is HIGH; Data Bus inputs are FLOATING Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0 mA/DQ A6 = 0, A2 = 1 mA/DQ A6 = 1, A2 = 0
IODTT
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet
20
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Electrical Characteristics
4
4.1
Table 12 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol Values Min. Max. 2.3 2.3 2.3 95 V V V % - 0.5 - 1.0 - 0.5 5 Unit Note/Test Condition
1) 1) 1) 1)
VIN, VOUT Voltage on VDD relative to VSS VDD Voltage on VDDQ relative to VSS VDDQ Storage Humidity (without condensation) HSTG
Voltage on any pins relative to VSS
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
Table 13 Parameter
Operating Conditions Symbol Values Min. Max. +65 +95 +100 +105 90 C C C kPa %
5) 1)2)3)4)
Unit
Notes
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
TOPR TCASE TSTG PBAR HOPR
0 0 -50 +69 10
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. 2) Within the DRAM Component Case Temperature Range all DRAM specifications will be supported 3) Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to
tREFI = 3.9 s
4) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 C Case Temperature before initiating Self-Refresh operation. 5) Up to 3000 m.
Table 14 Parameter
Supply Voltage Levels and DC Operating Conditions Symbol VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) Values Min. Nom. 1.8 1.8 0.5 x VDDQ -- -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5 V V V V V V A
3)
Unit
Notes --
1) 2)
Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5
IL
1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Data Sheet
21
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Electrical Characteristics
Table 15
Speed Grade Definition Speed Bins DDR2-533C -3.7 4-4-4 Symbol @ CL = 3 @ CL = 4 @ CL = 5 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- DDR2-400B -5 3-3-3 Min. 5 5 5 40 55 15 15 Max. 8 8 8 70000 -- -- -- Unit Notes
Speed Grade IFX Sort Name CAS-RCD-RP latencies Parameter Clock Frequency
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) only. 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until recognized as low. 5)
VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
4) The output timing reference voltage level is VTT.
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Max. +500 -- 0.55 -- 0.55 -- -500 2 0.45 3 0.45 WR + tRP -5 DDR2-400 3-3-3 Min. -600 2 0.45 3 0.45 WR + tRP Max. +600 -- 0.55 -- 0.55 -- ps Unit Notes1)
Table 16 Parameter
DQ output access time from CK / CK tAC CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) DQ and DM input hold time (single ended data strobe)
tCCD tCH tCKE tCL tDAL tDELAY
tCK tCK tCK tCK tCK
ns
tIS + tCK + tIH --
tIS + tCK + -- tIH
275 25 0.35 -500 -- -- -- +500
tDH(base) 225 tDH1(base) -25
0.35 -450
-- -- -- +450
ps ps
DQ and DM input pulse width (each tDIPW input) DQS output access time from CK / CK Data Sheet
tCK
ps
tDQSCK
22
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Electrical Characteristics Table 16 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Max. -- 300 0.35 -- WL - 0.25 -5 DDR2-400 3-3-3 Min. 0.35 -- Max. -- 350 Unit Notes1)
tDQSL,H tDQSQ
tCK
ps
Write command to 1st DQS latching tDQSS transition DQ and DM input setup time (differential data strobe)
WL + 0.25 WL - 0.25 WL + 0.25 tCK -- -- -- -- -- -- 150 25 0.2 0.2 37.5 50 -- 475 0.6 -- -- -- -- -- -- ps ps
tDS(base) 100
DQ and DM input setup time (single tDS1(base) -25 ended data strobe) DQS falling edge hold time from CK tDSH (write cycle) DQS falling edge to CK setup time (write cycle) Four Activate Window period Clock half period 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 375 0.6
tCK tCK
ns ns ps ps
2)3) 4)
tDSS tFAW
tHP Data-out high-impedance time from tHZ
CK / CK Address and control input hold time Address and control input pulse width (each input) DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS Data hold skew factor Average periodic refresh Interval
MIN. (tCL, tCH)
tAC.MAX
-- --
tAC.MAX
-- --
tIH(base) tIPW
tCK
Address and control input setup time tIS(base)
250 2 x tAC.MIN
--
350
--
ps ps ps
tLZ(DQ) tLZ(DQS) tMRD tOIT tQH tQHS tREFI
tAC.MAX tAC.MAX
-- 12 -- 400 7.8 3.9 -- -- 1.1 0.60
2 x tAC.MIN tAC.MAX
tAC.MIN
2 0
tAC.MIN
2 0
tAC.MAX
-- 12 -- 450 7.8 3.9 -- -- 1.1 0.60
tCK
ns
tHP - tQHS
-- -- -- 127.5 15 + 1tCK 0.9 0.40
tHPQ - tQHS
-- -- -- 127.5 15 + 1tCK 0.9 0.40
ps s s ns ns
5) 6)
Auto-Refresh to Active/Auto-Refresh tRFC command period Precharge-All (8 banks) command period Read preamble Read postamble
tRP tRPRE tRPST
tCK tCK
Data Sheet
23
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Electrical Characteristics Table 16 Parameter Timing Parameter by Speed Grade - DDR2-400B & DDR2-533C Symbol -3.7 DDR2-533 4-4-4 Min. Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Auto-Precharge Write recovery time for write with Auto-Precharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command WR Max. -- -- -- -- 0.60 -- 7.5 10 7.5 0.35xtCK 0.40 15 -5 DDR2-400 3-3-3 Min. 7.5 10 7.5 0.35xtCK 0.40 15 Max. -- -- -- -- 0.60 -- ns ns ns Unit Notes1)
tRRD tRTP
tWPRE tWPST Write recovery time for write without tWR
tCK tCK
ns
tWR/tCK
7.5 2 -- --
tWR/tCK
10 2 -- --
tCK
ns
tWTR tXARD
tCK
tXARDS
6 - AL
--
6 - AL
--
tCK
tXP
2
--
2
--
tCK
tXSNR
tRFC +10
200
-- --
tRFC +10
200
-- --
ns
Exit Self-Refresh to Read command tXSRD
2) x4 & x8 (1k page size)
tCK
1) For details and notes see the relevant INFINEON component data sheet 3) 8 bank device Sequential Activation Restriction. No more than 4 banks may be activated in a rolling tFAW window. 4) x16 (2k page size), not on 256 Mbit component 5) 0 TCASE 85 C 6) 85 C < TCASE 95 C
Data Sheet
24
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Electrical Characteristics
Table 17 Symbol
ODT AC Electrical Characteristics and Operating Conditions Parameter / Condition ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off Values Min. Max. 2 2 Unit Notes
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
tCK
ns ns
1)
tAC.MIN tAC.MAX + 1 ns tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
2.5 2.5
tCK
2)
tAC.MIN tAC.MAX + 0.6 ns ns ODT turn-off (Power-Down Modes) tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns ODT to Power Down Mode Entry Latency 3 -- tCK ODT Power Down Exit Latency 8 -- tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measure from tAOND. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
Data Sheet
25
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
SPD Codes
5
Table 18
SPD Codes
SPD Codes for HYS64T128020HM-[3.7/5]-A HYS64T128020HM-3.7-A HYS64T128020HM-5-A 1 GByte x64 2 Ranks (x16) PC2-3200M-333 Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 50 60 00 82 10 00 00 0C 08 38 00 08 00 01 50 60 50 Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
Product Type
Organization
1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2-4200M-444 Rev. 1.1 HEX 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 08 38 00 08 00 01 3D 50 50 26
tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tCK @ CLmax -2 (Byte 18) [ns]
Data Sheet
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
SPD Codes Table 18 SPD Codes for HYS64T128020HM-[3.7/5]-A HYS64T128020HM-3.7-A HYS64T128020HM-5-A 1 GByte x64 2 Ranks (x16) PC2-3200M-333 Rev. 1.1 HEX 60 3C 28 3C 28 80 35 47 15 27 3C 28 1E 00 00 37 7F 80 23 2D 00 55 58 32 1D 1C 16 16 Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
Product Type
Organization
1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Description
PC2-4200M-444 Rev. 1.1 HEX 60 3C 28 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 7F 80 1E 28 00 57 58 36 1C 1C 1C 27
tAC SDRAM @ CLmax -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2P (DT2P) T3N (DT3N) T3P.FAST (DT3P fast)
T2N (DT2N, UDIMM) or T2Q ( (DT2Q, RDIMM) 26
Data Sheet
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
SPD Codes Table 18 SPD Codes for HYS64T128020HM-[3.7/5]-A HYS64T128020HM-3.7-A HYS64T128020HM-5-A 1 GByte x64 2 Ranks (x16) PC2-3200M-333 Rev. 1.1 HEX 11 2C 1E 2B 00 00 00 00 11 27 C1 00 xx 36 34 54 31 32 38 30 32 30 48 4D 35 41 20 20 Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
Product Type
Organization
1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 54 55 56 57 58 59 60 61 62 63 64 65 - 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 Description T3P.slow (DT3P slow) T4R (DT4R) / T4R4W S Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 28
PC2-4200M-444 Rev. 1.1 HEX 14 36 1F 2D 00 00 00 00 11 D8 C1 00 xx 36 34 54 31 32 38 30 32 30 48 4D 33 2E 37 41
Data Sheet
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
SPD Codes Table 18 SPD Codes for HYS64T128020HM-[3.7/5]-A HYS64T128020HM-3.7-A HYS64T128020HM-5-A 1 GByte x64 2 Ranks (x16) PC2-3200M-333 Rev. 1.1 HEX 20 20 20 1x xx xx xx xx xx xx xx 00 Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
Product Type
Organization
1 GByte x64 2 Ranks (x16)
Label Code JEDEC SPD Revision Byte# 88 89 90 91 92 93 94 95 96 97 98 99 - 127 Description Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1) Module Serial Number (2) Module Serial Number (3) Module Serial Number (4) Not used
PC2-4200M-444 Rev. 1.1 HEX 20 20 20 1x xx xx xx xx xx xx xx 00
Data Sheet
29
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Package Outlines
6
Package Outlines
3.8 MAX. 2.3 MAX. 54 0.15 B 1.65 -0.25 0.1 C 2.275 0.025
2.6 0.1
2.3 0.2
0.62 0.03 3.525 0.025
5.525 0.025 (44.72) D B A 107 214 B 43.38 0.02
4.725 0.025
30 0.15
A
C 0.1 0.8 0.08
0.1 M C B M
106 x 0.4 = 42.4
(3.44)
(2.43)
0.4
108
1.15
2.3
Detail of contacts A-A E Contact Area B-B 1.3 0.02 0.1 M A B M
4.3
1
A
2.9
0.4
0.26 0.02
0.06 C D E 107x
GLD09638
Burnished, no burr allowed
Figure 3
Package Outline Raw Card A L-DIM-214-1
Data Sheet
30
1.08 -0.04
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
HYS64T128020HM-[3.7/5]-A Micro-DIMM DDR2 SDRAM Modules
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
7
Product Type Nomenclature (DDR2 DRAMs and DIMMs)
Infineon's nomenclature uses simple coding combined with some propriatory coding. Table 19 provides examples for module and component product type number as well as the field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 20 and for components in Table 21. Table 19 Nomenclature Fields and Examples Field Number 1 Micro-DIMM DDR2 DRAM Table 20 1 2 3 4 HYS HYB 2 64 18 3 T T 4 128 1G 5 0 16 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A
Example for
DDR2 DIMM Nomenclature Values Coding HYS 64 72 T 32 64 128 256 0 .. 9 Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte look up table 1, 2, 4 look up table look up table
Field Description INFINEON Modul Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1)
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
Table 21 1 2 3 4
DDR2 DRAM Nomenclature Values Coding HYB Constant SSTL1.8 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-533C DDR2-400B
Field Description INFINEON Component Prefix DRAM Technology
Interface Voltage [V] 18 T Component Density 256 [Mbit] 512 1G 2G
5 6 7 8 9
Raw Card Generation
Number of Module 0, 2, 4 Ranks Product Variations 0 .. 9 Package, Lead-Free Status Module Type A .. Z D M R U
5+6 Number of I/Os
40 80 16
7 SO-DIMM Micro-DIMM Registered Unbuffered PC2-4200 4-4-4 PC2-3200 3-3-3 First Second 11 10 9 8
Product Variations Die Revision Package, Lead-Free Status Speed Grade N/A for Components
0 .. 9 A B C F -3.7 -5
10 11
Speed Grade Die Revision
-3.7 -5 -A -B
Data Sheet
31
Rev. 1.0, 2004-10 04132004-S0LP-CL4Q
www.infineon.com
Published by Infineon Technologies AG

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